1. Field of the Disclosure
The present disclosure pertains to the field of signal transfer between components. More particularly, the present disclosure pertains to receiving and synchronizing signals that are transmitted in a source synchronous manner. In some cases, the signals may be transmitted at various frequency ratios with respect to a core frequency.
2. Description of Related Art
One limitation on the throughput of a computer or other processing system is the interface between integrated circuits and/or other components in the system. Interface circuits often provide synchronization between components operating with different clocking signals or at different clocking frequencies. Improved interface circuitry may allow faster signaling between various components.
In some cases, buses between components are unable to transfer data as rapidly as a component produces or requests data. One prior art mechanism for dealing with this problem is to provide a bus interface that operates at a lower frequency than a core portion of the component. For example, a number of Intel Pentium(copyright) Processors available from Intel Corporation of Santa Clara, Calif., have a core that operates at either even fractional multiplier (e.g., a 1:2, 1:3, etc., font side bus to core frequency ratio) or an odd fractional multiplier (e.g., a 2:3, 2:5, etc., front side bus to core frequency ratio). These processors, however, generally do not employ a source synchronous scheme for the front side interface with the system bus, nor do they employ a source synchronous bus that operates at an odd bus to core frequency ratio. The interface with the system bus may be referred to as a front side bus as a back side bus is typically an interface to a cache memory.
Some prior art processors include back side buses employing source synchronous signaling. In fact, such source synchronous signaling has been accomplished using even fractions (e.g., 1:2, 1:3, etc.) of the core clock frequency. One example is the Intel Pentium(copyright) II processor also available from Intel Corporation. In such prior art source synchronous signaling systems, data and one or more transfer clocks (also referred to as xe2x80x9cstrobesxe2x80x9d) are transmitted together.
One prior art approach to receiving and synchronizing source synchronous signals that may be used where the transmit clock operates at a different frequency than the core clock of the receiving device is shown in FIG. 1. In this approach, a set of deskew latches 110 receive data chunks from a data bus 105. In FIG. 1, only one data line and one corresponding set of latches is illustrated; however, these items are typically replicated to form a multi-bit bus.
STROBE and STROBE# signals from signal lines 115 and 120 pass through input buffers 125 and enter a latch control circuit 130. The latch control circuit 130 provides latch enable signals AEN, BEN, CEN, and DEN respectively on signal lines 135, 136, 137, and 138. The latch control circuit 130 generates these enable signals so that sequentially delivered data bits (e.g., from a burst cycle) are latched by deskew latches 112, 116, 114, and 118 in that order. To accomplish this, the latch control circuit 130 includes a STROBE triggered latch control circuit 132 that is a one bit counter triggered on STROBE to alternate selecting deskew latches 112 and 116. A STROBE# triggered latch control circuit 134 may be a one bit counter triggered on STROBE# to alternate selecting deskew latches 114 and 118. Accordingly, the circuit 132 alternates between capturing data with latches 112 and 114 on rising edges of strobe, and the circuit 134 alternates between capturing data with latches 116 and 118 on rising edges of STROBE#.
A selection control circuit 150 controls a selector circuit 140 (e.g., a multiplexer). The selection control circuit 150 provides a MUXSEL signal on a signal line 152 to select data from the deskew latches 110 to be driven to a core latch 160. The MUXSEL signal is driven by core-clocked logic that anticipates the return of data based on when requests are made and knowledge of the data return latency. The MUXSEL signal sequentially selects the four deskew latches to provide the data received from the data bus 105 to the core latch 160 in the desired order.
In this arrangement, timing constraints may affect the ability of the core to latch data signals received from the data bus 105. Typically, buffering is employed to receive signals in both the case of the data bus (buffer 107) and the strobe signals (buffers 125). Additionally, the latch control circuit 130 introduces delay into the strobe path. Since matching clock (strobe) and data signal timing is typically an important facet of source synchronous communication since it impacts the burst rate, a delay match circuit 109 may be introduced to match the delay of the latch control circuit 130 and assist in providing the data and the clocking signals to the deskew latches 110 approximately simultaneously.
Thus, data from the data bus 105 passes through a lengthy path including the buffer 107, the delay match circuit 109, a deskew latch, and the selector circuit 140 before the core latch 160 is reached. This prior art technique may not provide a sufficiently low delay path to the core for data received from the data bus in a source synchronous signaling environment. It may be especially advantageous to reduce this path and accordingly allow the core more time for processing of data signals received from the data bus as higher core and data transmission frequencies are achieved.
A disclosed apparatus includes a core portion clocked by a core clock and an interface circuit. The interface circuit is coupled to deliver a burst cycle to said core portion. The burst cycle includes a set of sequentially delivered bits that are transmitted with corresponding sequential edges of a transfer clock. Each bit of the burst cycle is delivered either via one of a set of receiving latches coupled in parallel to a data input or via a bypass path that bypasses the set of receiving latches.